The present application claims priority under 35 U.S.C. xc2xa7119 to Korean Patent Application No. 00-55205 filed on Sep. 20, 2000, the entire contents of which are hereby incorporated by reference for all purposes.
1. Field of the Invention
The present invention relates to a method of polishing a wafer by chemical mechanical polishing (CMP), and more particularly, to a method of controlling wafer polishing time using a sample skip algorithm and a wafer polishing method using the same.
2. Description of the Related Art
Recent progress in high integration of semiconductor devices has lead to ultra-miniaturization. The patterns created for the ultra-miniaturization result in a large step difference in a layer on top of the pattern between a region having the pattern thereon and a region not having the pattern. Due to the miniature structure semiconductor device and its attendant small design rules, precise control of all manufacturing processes to create such devices becomes increasingly important. These manufacturing processes include lithography, etching, chemical vapor deposition (CVD) processes, CMP and the number of times the CMP process is used. The CMP time is determined by the amount to be removed from the initial thickness of a layer being polished on a wafer to the target thickness thereof, and the removal rate of a polishing equipment.
According to conventional CMP processes, the removal rate is obtained by performing a CMP process on a blanket wafer for a predetermined time. In high volume production, such as a mass production line, it is not actually possible to frequently monitor the polished thickness during a CMP process. Thus, each time the CMP process is performed on one lot consisting of a plurality of wafers, a CMP process on a sample wafer to measure a polishing rate, the CMP time is determined based on data resulting therefrom to perform the CMP process on a main lot. However, conventional CMP processes are not only time consuming due to a sample check made for each lot, but also tend to make inaccurate determinations on the CMP time affected by the operator""s perspective. Thus, it is highly desirable to develop a general-purpose sample-skip type CMP process which does not require a sample check step. The elimination of the sample check step results in a time-efficient process which reduces processing time.
Furthermore, accurate prediction of CMP time is difficult in conventional CMP processes, due to thickness variations appearing in a layer being polished on each wafer before the CMP process and the removal rate variation attendant on restrictions on the structure of a polishing equipment itself. This is further complicated by the large step difference in miniaturized patterns noted above. For these reasons, research into improving CMP process capability using endpoint detection (EPD) or advanced process control (APC) are ongoing.
Representative approaches adopting EPD include using optical principles such as optical interferometry and reflection, and examining motor current changes depending on the difference of friction between layers. However, a method adopting EPD is applicable only to shallow trench isolation (STI) and polishing of a first interlevel insulating layer and a metal layer. It is difficult to adopt in a CMP process for other insulating layers or inter-metal insulating layers due to the complexity of underlying layers.
Furthermore, in a method adopting APC, process control is applied to a semiconductor process to interpret each unit process and organically combines them to thereby transmit actual run data in a feed-back or feed-forward manner, allowing for a run-to-run control while real-time monitoring equipment and process variables. Adopting APC during a CMP process necessitates modeling of the CMP mechanism and creation of a closed loop control (CLC) system. Studies on accurate modeling of a CMP process and its combination with in-line metrology tool are ongoing for a CMP run-to-run control by APC. However, studies made heretofore overlook differences between each polishing head in a multi-head polishing equipment, thus making application to a polishing equipment in current use for mass production unsuitable.
The present invention is therefore directed to a method of controlling wafer polishing time and a wafer polishing method using the same which substantially overcomes one or more of the problems due to the limitations and disadvantages of the related art.
To solve at least one of the above and other problems, it is an object of the present invention to provide a method of controlling a polishing time of a next lot of wafers by using an algorithm for determining the variable removal rate from the relationship of chemical mechanical polishing (CMP) process data for an actual patterned wafer of a previous lot and the removal rate of a layer being polished on a blanket wafer essential for prediction of a CMP time, in order to realize a sample-skip type CMP process.
It is another object of the present invention is to provide a method of controlling a wafer polishing time, by which a CMP time for a next lot of wafers can be precisely predicted employing an algorithm for effectively reflecting the removal rate of a polished layer which continuously varies depending on equipment features during the polishing process.
It is still another object of the present invention is provide a method of minimizing a variation range between lots which may be widened by using a plurality of heads included in a multi-head type CMP equipment.
It is yet still another object of the invention to provide a method of polishing a wafer using a sample-skip algorithm in which a sample test step is skipped.
Accordingly, to achieve at least one of the above and other objects, the present invention is directed to a method of controlling the polishing time of a wafer. According to the method, a chemical mechanical polishing (CMP) process is performed on a plurality of wafers of an n-th lot among a plurality of lots, each lot consisting of a plurality of wafers, for a time xcex94t(n), to calculate the amount removed xcex94ToxP(n) from a polished layer on the wafer. The removal rate RRb(n) of a layer on a blanket wafer is calculated from the amount removed xcex94ToxP(n). A CMP time xcex94t(n+1) is determined for wafers of an n+1-th lot using the relationship equation xcex94t(n+1)={xcex94ToxT(n+1)+A}/RRb(n) where xe2x80x9cAxe2x80x9d is a constant and xcex94toxT(n+1) is the target amount of a layer to be removed from a wafer of an n+1-th lot.
The removal rate RRb(n) of the layer on the blanket wafer is calculated using the relationship equation RRb(n)={xcex94ToxP(n)+A}/xcex94t(n), where xe2x80x9cAxe2x80x9d is a constant. The constant xe2x80x9cAxe2x80x9d is determined by xcex94ToxB=a*xcex94ToxP+A which is the relationship equation of a thickness variation xcex94ToxP between before and after CMP on polished layers on wafers of the plurality of lots and a thickness variation xcex94ToxB after CMP on a polished layer on a blanket wafer. If the polished layers on the wafers of the plurality of lots are all formed of the same material, xe2x80x9caxe2x80x9d is substantially 1.
The removal rate RRb(n) of the layer on the blanket wafer maybe obtained from a weighted average value for one or more removal rate data selected from RRb(1), RRb(2), RRb(3), . . . RRb(n).
A CMP process is performed on one wafer selected among wafers of a first lot for a time xcex94t(s) to obtain the amount removed xcex94ToxP(s) from a polished layer on the selected wafer, where n=1. The removal rate RRb(s) of the polished layer on the selected wafer is calculated from the amount removed xcex94ToxP(s) by using the relationship equation RRb(s)={xcex94ToxP(s)+A}/xcex94t(s), where xe2x80x9cAxe2x80x9d is a constant. A CMP time xcex94t(1) of wafers of the first lot is determined from a target amount xcex94ToxT(1) of a layer to be removed from the wafers of the first lot, using the relationship equation xcex94t(1)={xcex94ToxT(1)+A}/RRb(s), where xe2x80x9cAxe2x80x9d is a constant.
At least one of the above and other objects may be created by a method of polishing a wafer. According to the polishing method, the removal rate RRb(n) of a layer on a blanket wafer is calculated from chemical mechanical polishing (CMP) process data for a plurality of wafers of an n-th lot, among a plurality of lots, each lot consisting of a plurality of wafers. A CMP time xcex94t(n+1) of wafers of an n+1-th lot is determined from the target amount xcex94ToxT(n+1) of a polished layer to be removed from the wafer of the n+1-th lot, using the relationship equation xcex94t(n+1)={xcex94ToxT(n+1)+A}/RRb(n), where xe2x80x9cAxe2x80x9d is a constant. A CMP process is performed on a plurality of wafers of the n+1-th lot for the time xcex94t(n+1).
The calculating of the removal rate RRb(n) of the layer on the blanket wafer includes performing a CMP process on the wafers of the n-th lot for a time xcex94t(n) to calculate the amount removed xcex94ToxP(n) from a polished layer on the wafer, and calculating the removal rate RRb(n) from the amount removed xcex94ToxP(n).
A wafer polishing method according to the present invention involves sequentially performing a CMP process on a plurality of wafers constituting each lot by two or more wafers using a CMP equipment including two or more heads.
The present invention makes possible a CMP process for in situ controlling a CMP time of the following lot with a closed loop control (CLC) system in a sample-skip manner using an algorithm for calculating a variable removal rate set with a weighting factor while minimizing the range of differences between lots which may be widened by using a plurality of heads in a multi-head type equipment, thereby effectively reducing fluctuations in the removal rate between heads. Furthermore, regardless of product types of a wafer polished in the preceding run, the invention allows a CMP process to be performed for various kinds of products.
These and other objects of the present invention will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating the preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.